In modern electronic systems, from the perspective of bandwidth and performance, a master device, e.g., a controller, a microprogrammed control unit (MCU), and the like, does not generally connect to only one slave device. Multiple devices are generally coupled to an input/output (I/O) bus. In such configuration, only a master slave or a slave device is active to drive the bus at a given time.
The following conditions can lead to undesirable bus behavior: (1) manufacturing defects or system failure; (2) more than one device drives the bus at the same time, or no device drives the bus.
Conventional bus contention detection circuits include two receiver modules and a logic unit, each of the receiver modules includes a threshold range and receives a signal from the bus and outputs the signal to the logic unit. The logic unit determines a bus contention condition based on which signal is within the threshold range of the receiving modules. However, conventional bus contention detection circuits are constrained by the receiver modules' circuit structure, which restricts the internal threshold range, resulting in a relatively low detection accuracy. The receiver modules and the logic unit also require additional enable signals from core logic that further restrict the applicability of the bus contention detection circuits. For example, when the core logic fails, the detection circuit does not operate properly and fails to detect the bus contention condition on time.